The demand for solid-state electronics has increased exponentially since the 1950's, mainly due to the public's desire for smaller and faster products. To meet this need, solid-state manufacturers have continuously down-sized their products beyond what is visible to the naked eye. The sizes have become so small that they are often limited by the molecular properties of the material from which they are created. Furthermore, the manufacturing tolerances for the devices are even smaller. When manufacturing a product at this microscopic level, a slight variation in the allowable tolerances can reduce product quality or even make it nonfunctional. This poses a major problem for the production of semiconductors.
Manufacturers spend large amounts of money on controlling their processes to ensure that a high quality product is produced. Each step of the process is closely monitored to verify that the process is within certain manufacturing tolerances. These tolerances are defined so that the margin of variance does not put the final product in jeopardy. To better comprehend the complexities of the issues surrounding manufacturing tolerances, it is important to understand how the products are constructed.
Semiconductor devices begin life in a molten mixture from which a pure seed crystal is placed into and drawn from, creating a structured crystal ingot. The ingot is then sliced into thin pieces called “wafers”. The wafers are used as the base structure for creating layers of material with varying properties. This variance in properties is what creates different types of semiconductor characteristics. The small sizes require the use of highly precise machines for tooling the wafers. In order for the machinery to maintain this precision, test wafers are created from the group of sliced wafers. These test wafers are generally marked with critical dimensions that can be measured by the machines.
One type of these machines is the Critical Dimension Scanning Electron Microscope (CD SEM). It is used to measure extremely small dimensions marked on the test wafers. These dimensions can then be used to calibrate the tooling machines necessary for production. Generally, the CD SEM is used to gauge production quality after individual fabrication processing has occurred. It is not uncommon to have multiple CD SEMs in a fabrication environment. This drives a strong need to have the CD SEMs consistently match within a predetermined specification. It may be necessary to check the CD SEM parameters on a daily basis to ensure it is within the desired tolerance.
When a new machine is brought into the manufacturing process, great care is taken to qualify its parameters. Any machine, no matter how precise, will always have a certain amount of deviation in accuracy. To offset this fact, the new machine is analyzed to make sure it meets the equipment specifications necessary to perform a particular aspect of a semiconductor development phase. Once the machine is incorporated into the manufacturing process, it must be continually monitored to protect against equipment drift and alterations in materials or in the environment. All manufacturing processes are inherently unstable and must be rigidly monitored to avoid ruining the end product.
Often, the manufacturing process will require different types of fabrication or “fab” to complete a single device. For various economic reasons, these fab facilities may not be physically located near each other. The fabs might even reside in different countries. Devices, such as a test wafer, used for calibrating the tooling machinery will need to be shipped between locations. Problems associated with device transporting are further compounded due to the fact that some fabs require repeated exchanges of test wafers to maintain tolerances between the facilities. Production for a particular machine may have to cease while the test wafer is being transported. This causes lower output and increased average cost for the manufactured device. Additionally, transit time for the test wafer prevents any “real time” synchronizing between facilities. Another detrimental side effect is that anytime a device has to be moved from place to place, the odds of it becoming lost or accidentally damaged increase dramatically. If this occurs, it creates an enormous cost both in time and money due to downtime and the reconfiguration of new test wafers.